2 906 734 libros electrónicos en 110 idiomas
¿No le conviene? No hay problema. Puedes devolver los artículos hasta 30 días
No se equivocará con un vale de regalo. El destinatario puede elegir cualquier producto de nuestra oferta.
Hasta 30 días para devoluciones
This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly.In an appendix all programs to compute the cost and cycle time of the designs described are listed in C code. Running these simple C programs on a PC is sufficient to verify the results presented. The book addresses design professionals and students in computer architecture.
¡Hola! Soy Libroamiko, tu asesor de libros.
¿Cómo puedo ayudarte?